ww3-gpu Port Lifecycle

ww3-gpu Port Lifecycle A lifecycle diagram generated by Archify. Ledger levels Replay steps (status) Default on (ADR-0013) Fortran only · 713 of 1023 routines · Ledger levels · 713 of 1023 01 Fortran only 713 of 1023 routines 713 of 1023 Claimed · 0 rows open · Ledger levels · 0 rows 02 Claimed 0 rows open 0 rows Translated · 310 (250 not wired) · Ledger levels · 310 (250 only) 03 Translated 310 (250 not wired) 310 (250 only) Wired · 60 (50 not regtested) · Ledger levels · 60 (50 only) 04 Wired 60 (50 not regtested) 60 (50 only) Regtested · 10 routines · Ledger levels · 10 05 Regtested 10 routines 10 L2 · 2: W3SNL1, INSNL1 · Replay steps (status) · 2: SNL1, INSNL1 L2 2: W3SNL1, INSNL1 2: SNL1, INSNL1 gpu · 0 routines · Replay steps (status) · 0 gpu 0 routines 0 Default, host · 0 parts, OpenMP · Default on (ADR-0013) · 0 parts Default, host 0 parts, OpenMP 0 parts Default, device · 0 parts, CUDA SRCE · Default on (ADR-0013) · 0 parts Default, device 0 parts, CUDA SRCE 0 parts claim row ports.tsv row fork pin calls it validation phase L2 replay CUDA, owner timing parity batched, bits Legend initial state active waiting decision success neutral final state